The present invention relates to a SRAM (Static Random Acess Memory) having a high operational speed.
FIG. 9 is a circuit diagram illustrating a first conventional example of a memory cell configuration of the SRAM.
Referring to FIG. 9, the memory cell 200 has an inverter latch configured with a pair of nMOS (n-channel Metal Oxide Semiconductor) driver transistors 23 and 24 together with a pair of pMOS (p-channel MOS) load transistors 25 and 26. Each of a pair of memory terminals of the inverter latch is connected to each of a pair of bit lines D0 and D0 though each of nMOS access transistors 21 and 22. Gates of the nMOS access transistors 21 and 22 are connected a word line WL0.
A plurality of memory cells having the same configuration with the memory cell 200 are arrayed in lateral and longitudinal directions of FIG. 9 sharing each word line laterally, and each pair of bit lines longitudinally.
Although not depicted in the drawing, a common well of the nMOS access transistors 21 and 22 and the nMOS driver transistors 23 and 24 is fixed to a ground voltage, and a common well of the pMOS load transistors 25 and 26 are fixed to a power supply voltage, in the same way with ordinary CMOS (Complementary MOS) cirucits.
When the memory cell 200 is selected, that is, the word line WL0 is turned to HIGH by a word driver 10, data latched in the inverter 25 latch is exchanged with outside by way of the nMOS access transistors 21 and 22 becoming ON through the pair of bit lines D0 and D0, which means that the read/wirte speed of the memory cell 200 depends on the on-current of the nMOS access transistors 21 and 22. Therefore, in many conventional SRAMs, a boosted voltage Vpp higher than the power supply voltage is supplied to the word driver 10 in order to improve the read/write speed by raising the word line voltage to be supplied to gate terminals of the nMOS access transistors 21 and 22, such as shown in FIG. 10 illustrating a second conventional example of the memory cell configuration.
On the other hand, the on-current of the nMOS driver transistors 23 and 24 should be sufficiently large compared to the on-current of the nMOS access transistors 21 and 22, for stably maintaining latched status during reading operation of the memory cell 200. However, while the on-current of the nMOS access transistors 21 and 22 is increased in the second conventional example of FIG. 10 compared to the first conventional example of FIG. 9, the on-current of the nMOS driver transistors 23 and 24 is left to be the same. Therefore, the data maintenance stability is degraded in the second conventional example of FIG. 10.
Furthermore, the boosted voltage Vpp, which is usually generated by way of a charge pump circuit, for example, needs large capacitors, requiring considerable LSI chip areas.
FIG. 11 is a circuit diagram illustrating a third conventional example of the memory cell configuration, which is disclosed in a Japanese patent application laid open as a Provisional Publication No. 211079/'95.
In the third conventional example of FIG. 11, a back-bias supplier circuit 13 is provided for supplying a back-bias voltage to the wells of nMOS access transistors 21 and 22 and the nMOS driver transistors 23 and 24 of the memory cells. The back-bias supplier circuit 13 outputs either the ground voltage or a negative voltage (-2V, for example,) which is generated by a charge pump circuit.
Another characteristic of the memory cell 201 of FIG. 11 is that the transistors having low threshold voltage (0.4V, for example,) are applied there.
When the threshold voltage becomes low, the on-current of the MOS transistor becomes large, and, at the same time, the sub-threshold current, that is, the leak current flowing through the MOS transistor of OFF state, increses more sharply than the on-current. Therefore, a high-speed read/write operation is realized making use of the large on-current of the low threshold voltage MOS transistors, in the memory cell 201 of the third conventional example, and when the memory cell 201 is not in operation, the threshold voltage of the nMOS access transistors 21 and 22 and the nMOS driver transistors 23 and 24 is made high (0.9V, for example) by supplying the negative voltage to p-well thereof from the back-bias supplier circuit 13, for reducing the sub-threshold voltage flowing through them.
However, the negative voltage should be supplied to p-wells of all memory cells in the third conventional example of FIG. 11, while boosted voltage Vpp is sufficient to be supplied to a single selected word line. Therefore, a high power is needed for switching the SRAM from operation mode into non-operation mode, in the third conventional example of FIG. 11, together with a long time needed for mode switching, which restricts flexible switching into the non-operation mode.
Furthermore, the back-bias supplier circuit 13 should continue to generate the negative voltage during the non-operation mode of the SRAM, which counteracts a part of the effect of reducing the sub-threshold current.
FIG. 12 is a circuit diagram illustrating a fourth conventional example of the memory cell configuration disclosed in a Japanese patent application laid open as a Provisional Publication No. 296587/'95.
In this memory cell 202 of FIG. 12, source terminals of the nMOS driver transistors 23 and 24 are connected to a common source line Vss, and the well of the nMOS access transistors 21 and 22 and nMOS driver transistors 23 and 24 is connected to a ground line GND. Between the common source line Vss and the ground line GND, an nMOS transistor 36 and a high-resistance element 37 are connected in parallel.
Also in the memory cell 202, the low threshold voltage MOS transistors are used for the nMOS access transistors 21 and 22 and the nMOS driver transistors 23 and 24.
In the read/write operation, the nMOS transistor 36 is turned to ON by a chip enable signal CE supplied to its gate terminal. Therefore, the potential of the common source line Vss becomes the same with the potential of the ground line GND, and the nMOS access transistors 21 and 22 and the NMOS driver transistors 23 and 24 operate at high speed as ordinary low threshold voltage MOS transistors.
When the memory cell 202 is not in operation, the nMOS transistor 36 is controlled to be OFF, and the common source line Vss is connected to the ground line GND only through the high-resistance element 37. The unnecessary sub-threshold current leaking through the nMOS driver transistors 23 and 24 flows to the ground line GND through the high-resistance element 37. By the sub-threshold current flowing through the high-resistance element 37, the potential of the common source line Vss is made somewhat higher than the ground line GND. Therefore, the well potential of the nMOS driver transistors 23 and 24 is made substantially lower than potential of their source terminals, and makes their threshold voltage high, restricting the sub-threshold current.
However, for realizing the above high-speed operation, the nMOS transistor 36 should be large enough to give a sufficiently low on-resistance, and should have a sufficiently small sub-threshold current, at the same time.
As heretofore described, various devices have been disclosed for improving operational speed of the SRAM memory cell. However, there are problems left in the conventional examples.
A problem is increase of the number of circuit elements, such as charge pump circuits provided in the second and the third conventional examples of FIGS. 10 and 11, or the nMOS transistor 36 and the high-resistance element 37 for controlling standby current provided in the fourth conventional example of FIG. 12.
Another problem is increase of the chip size because of the additional elements, such as the large capacitors to be used in the charge pump circuits of the second and the third conventional examples, or the nMOS transistor 36, used for a chip enable switch in the fourth conventional example, which requires a considerably large chip space because it must shunt the high-resistance element 37 with very little voltage difference between its source terminal and drain terminal.
Another problem is intricacy of circuit designing, because precise consideration of characteristic dispersion of elements accompanying fabrication processes is to be required for designing analog circuits, such as the charge pump circuits of the second and the third conventional examples, or the standby current control circuit of the fourth conventional example.
Still another problem is the sub-threshold current still flowing through un-selected memory cells in the SRAMs of the third and the fourth conventional examples. The sub-threshold current of the nMOS access transistors may result in charge exchange between the bit-lines and the un-selected memory cells, without saying of the unnecessary power consumption. Usually, several hundreds to several thousands un-selected memory cells are connected to a pair of bit-lines. Therefore, the charge exchange of the un-selected memory cells may become not negligible compared to on-current of the selected memory cell. This means the reading speed of the SRAM varies depending on data pattern stored in the memory cells.